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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad976/ad976a one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 16-bit, 100 ksps/200 ksps bicmos a/d converters functional block diagram ref v ana 4k v r d15 d0 dgnd byte r/ c cs busy v dig v in agnd2 cap agnd1 2.5v reference 4r control logic & internal calibration circuitry clock parallel interface switched cap adc ad976/ad976a 4r 3 r = 6k v ad976 r = 3k v ad976a features fast 16-bit adc 200 ksps throughput C ad976a 100 ksps throughput C ad976 single 5 v supply operation input range: 6 10 v 100 mw max power dissipation choice of external or internal 2.5 v reference high speed parallel interface on-chip clock 28-lead skinny dip, ssop or soic packages general description the ad976/ad976a is a high speed, low power 16-bit a/d converter that operates from a single 5 v supply. the part con- tains a successive approximation, switched capacitor adc, an internal 2.5 v reference and a high speed parallel interface. the adc is factory calibrated to minimize all linearity errors. the analog full-scale input is the standard industrial range of 10 v. the ad976/ad976a is comprehensively tested for ac param- eters such as snr and thd, as well as the more traditional parameters of offset, gain and linearity. the ad976/ad976a is fabricated on analog devices propri- etary bicmos process, which has high performance bipolar devices along with cmos transistors. the ad976/ad976a is available in skinny 28-lead dip, ssop and soic packages. product highlights 1. fast throughput. the ad976/ad976a is a high speed (100 ksps/200 ksps throughput rates respectively), 16-bit adc based on a switched capacitor architecture. 2. single-supply operation. the ad976/ad976a operates from a single 5 v supply and dissipates only 100 mw max. 3. comprehensive dc and ac specifications. the ad976/ad976a is factory calibrated and fully tested for snr and thd as well as the traditional specifications of offset, gain and linearity. 4. complete a/d solution. the ad976/ad976a offers a highly integrated solution containing an accurate adc, reference and on-chip clock.
ad976/ad976a C2C rev. c ad976aCspecifications ad976aa ad976ab ad976ac parameter min typ max min typ max min typ max units resolution 16 16 16 bits analog input voltage range 10 10 10 v impedance 13 13 13 k w capacitance 22 22 22 pf throughput speed complete cycle 5 5 5 m s throughput rate 200 200 200 khz dc accuracy integral linearity error 3 2 3 lsb 1 differential linearity error C2 +3 C1 +1.75 2 lsb no missing codes 15 16 15 bit transition noise 2 1.0 1.0 1.0 lsb full-scale error 3, 4 0.5 0.25 0.5 % full-scale error drift 7 7 7 ppm/ c full-scale error, ext. ref = 2.5 v 0.5 0.25 0.5 % full-scale error drift, ext. ref = 2.5 v 2 2 2 ppm/ c bipolar zero error 4 10 10 15 mv bipolar zero error drift 2 2 2 ppm/ c power supply sensitivity v ana = v dig = v d = 5 v 5% 8 8 8 lsb ac accuracy spurious free dynamic range 5 90 96 90 db 6 total harmonic distortion 5 C90 C96 C90 db signal to (noise + distortion) 5 83 85 83 db C60 db input 27 28 27 db signal to noise 5 83 85 83 db full-power bandwidth 7 1 1 1 mhz input bandwidth 2.7 2.7 2.7 mhz sampling dynamics aperture delay 40 40 40 ns transient response full-scale step 1 1 1 m s overvoltage recovery 8 150 150 150 ns reference internal reference voltage 2.48 2.5 2.52 2.48 2.5 2.52 2.48 2.5 2.52 v internal reference source current 1 1 1 m a external reference voltage range for specified linearity 2.3 2.5 2.7 2.3 2.5 2.7 2.3 2.5 2.7 v external reference current drain ext. ref = 2.5 v 100 100 100 m a digital inputs logic levels v il C0.3 +0.8 C0.3 +0.8 C0.3 +0.8 v v ih +2.0 v dig + 0.3 +2.0 v dig + 0.3 +2.0 v dig + 0.3 v i il 10 10 10 m a i ih 10 10 10 m a notes 1 lsb means least significant bit. with a 10 v input, one lsb is 305 m v. 2 typical rms noise at worst case transitions and temperatures. 3 measured with fixed resistors as shown in figure 5 (ad976) and figure 6 (ad976a). adjustable to zero as shown in figure 7. 4 full-scale error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scal e transition voltage and includes the effect of offset error. the full-scale error is the worst case of either the Cfull-scale or +full-scale code transition voltage errors . 5 f in = 20 khz (ad976) and f in = 45 khz (ad976a), 0.5 db down, unless otherwise noted. 6 all specifications in db are referred to a full scale 10 v input. 7 full-power bandwidth is defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 db or 10 b its of accuracy. 8 recovers to specified performance after a 2 f s input overvoltage. specifications subject to change without notice. (C40 8 c to +85 8 c, f s = 200 khz, ref = internal reference, v dig = v ana = +5 v unless otherwise noted)
C3C rev. c ad976/ad976a ad976Cspecifications ad976a ad976b ad976c parameter min typ max min typ max min typ max units resolution 16 16 16 bits analog input voltage range 10 10 10 v impedance 23 23 23 k w capacitance 22 22 22 pf throughput speed complete cycle 10 10 10 m s throughput rate 100 100 100 khz dc accuracy integral linearity error 3 2 3 lsb 1 differential linearity error C2 +3 C1 +1.75 2 lsb no missing codes 15 16 15 bit transition noise 2 1.0 1.0 1.0 lsb full-scale error 3, 4 0.5 0.25 0.5 % full-scale error drift 7 7 7 ppm/ c full-scale error, ext. ref = 2.5 v 0.5 0.25 0.5 % full-scale error drift, ext. ref = 2.5 v 2 2 2 ppm/ c bipolar zero error 4 10 10 15 mv bipolar zero error drift 2 2 2 ppm/ c power supply sensitivity v ana = v dig = v d = 5 v 5% 8 8 8 lsb ac accuracy spurious free dynamic range 5 90 96 90 db 6 total harmonic distortion 5 C90 C96 C90 db signal to (noise + distortion) 5 83 85 83 db C60 db input 27 28 27 db signal to noise 5 83 85 83 db full-power bandwidth 7 700 700 700 khz input bandwidth 1.5 1.5 1.5 mhz sampling dynamics aperture delay 40 40 40 ns transient response full-scale step 2 2 2 m s overvoltage recovery 8 150 150 150 ns reference internal reference voltage 2.48 2.5 2.52 2.48 2.5 2.52 2.48 2.5 2.52 v internal reference source current 1 1 1 m a external reference voltage range for specified linearity 2.3 2.5 2.7 2.3 2.5 2.7 2.3 2.5 2.7 v external reference current drain ext. ref = 2.5 v 100 100 100 m a digital inputs logic levels v il C0.3 +0.8 C0.3 +0.8 C0.3 +0.8 v v ih +2.0 v dig + 0.3 +2.0 v dig + 0.3 +2.0 v dig + 0.3 v i il 10 10 10 m a i ih 10 10 10 m a notes 1 lsb means least significant bit. with a 10 v input, one lsb is 305 m v. 2 typical rms noise at worst case transitions and temperatures. 3 measured with fixed resistors as shown in figure 5 (ad976) and figure 6 (ad976a). adjustable to zero as shown in figure 7. 4 full-scale error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scal e transition voltage and includes the effect of offset error. the full-scale error is the worst case of either the Cfull-scale or +full-scale code transition voltage errors . 5 f in = 20 khz (ad976) and f in = 45 khz (ad976a), 0.5 db down, unless otherwise noted. 6 all specifications in db are referred to a full scale 10 v input. 7 full-power bandwidth is defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 db or 10 b its of accuracy. 8 recovers to specified performance after a 2 f s input overvoltage. specifications subject to change without notice. (C40 8 c to +85 8 c, f s = 100 khz, ref = internal reference, v dig = v ana = +5 v unless otherwise noted)
ad976/ad976a C4C rev. c all grades parameter conditions min typ max units digital outputs data format parallel 16 bits data coding binary twos complement v ol i sink = 1.6 ma +0.4 v v oh i source = 500 m a+4 v leakage current high-z state, 5 m a v out = 0 v to v dig output capacitance high-z state 15 pf digital timing bus access time 83 ns bus relinquish time 83 ns power supplies specified performance v dig 4.75 5 5.25 v v ana 4.75 5 5.25 v i dig 3.0 ma i ana 11 ma power dissipation 100 mw temperature range specified performance C40 +85 c specifications subject to change without notice. timing specifications (ad976a: f s = 200 khz; ad976: f s = 100 khz; C40 8 c to +85 8 c, v dig = v ana = +5 v unless othe rwise noted) symbol min typ max units convert pulsewidth t 1 50 ns data valid delay after r/ c low (ad976a/ad976) t 2 4.0/8.0 m s busy delay from r/ c low t 3 83 ns busy low (ad976a/ad976) t 4 4.0/8.0 m s busy delay after end of conversion (ad976a/ad976) t 5 180/360 ns aperture delay t 6 40 ns conversion time (ad976a/ad976) t 7 3.8/7.6 4.0/8.0 m s acquisition time t 8 1.0/2.0 m s bus relinquish time t 9 10 35 83 ns busy delay after data valid (ad976a/ad976) t 10 50 180/360 ns previous data valid after r/ c low (ad976a/ad976) t 11 3.7/7.4 m s throughput time (ad976a/ad976) t 7 + t 8 5/10 m s r/ c to cs setup time t 12 10 ns time between conversions (ad976a/ad976) t 13 5/10 m s bus access and byte delay t 14 10 83 ns specifications subject to change without notice.
ad976/ad976a C5C rev. c absolute maximum ratings 1 analog inputs v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 v cap . . . . . . . . . . . . . . . . +v ana + 0.3 v to agnd2 C 0.3 v ref . . . . . . . . . . . . . . . . . . . . . indefinite short to agnd2 ground voltage differences dgnd, agnd1, agnd2 . . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages v ana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v dig to v ana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v dig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v digital inputs . . . . . . . . . . . . . . . . . . . C0.3 v to v dig + 0.3 v internal power dissipation 2 pdip (n), soic (r), ssop (rs) . . . . . . . . . . . . . 700 mw junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c storage temperature range (n, r, rs) . . . C65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 28-lead pdip: q ja = 74 c/w; q jc = 24 c/w, 28-lead soic: q ja = 72 c/w; q jc = 23 c/w, 28-lead ssop: q ja = 109 c/w; q jc = 39 c/w. ordering guide temperature max min throughput package package model range inl s/(n+d) rate descriptions options ad976an C40 c to +85 c 3.0 lsb 83 db 100 ksps 28-lead, 300 mil plastic dip n-28b ad976bn C40 c to +85 c 2.0 lsb 85 db 100 ksps 28-lead, 300 mil plastic dip n-28b ad976cn C40 c to +85 c 83 db 100 ksps 28-lead, 300 mil plastic dip n-28b ad976aan C40 c to +85 c 3.0 lsb 83 db 200 ksps 28-lead, 300 mil plastic dip n-28b ad976abn C40 c to +85 c 2.0 lsb 85 db 200 ksps 28-lead, 300 mil plastic dip n-28b ad976acn C40 c to +85 c 83 db 200 ksps 28-lead, 300 mil plastic dip n-28b ad976ar C40 c to +85 c 3.0 lsb 83 db 100 ksps 28-lead small outline package r-28 ad976br C40 c to +85 c 2.0 lsb 85 db 100 ksps 28-lead small outline package r-28 ad976cr C40 c to +85 c 83 db 100 ksps 28-lead small outline package r-28 ad976aar C40 c to +85 c 3.0 lsb 83 db 200 ksps 28-lead small outline package r-28 ad976abr C40 c to +85 c 2.0 lsb 85 db 200 ksps 28-lead small outline package r-28 ad976acr C40 c to +85 c 83 db 200 ksps 28-lead small outline package r-28 ad976ars C40 c to +85 c 3.0 lsb 83 db 100 ksps 28-lead shrink small outline package rs-28 ad976brs C40 c to +85 c 2.0 lsb 85 db 100 ksps 28-lead shrink small outline package rs-28 ad976crs C40 c to +85 c 83 db 100 ksps 28-lead shrink small outline package rs-28 ad976aars C40 c to +85 c 3.0 lsb 83 db 200 ksps 28-lead shrink small outline package rs-28 ad976abrs C40 c to +85 c 2.0 lsb 85 db 200 ksps 28-lead shrink small outline package rs-28 ad976acrs C40 c to +85 c 83 db 200 ksps 28-lead shrink small outline package rs-28 pin configuration dip, soic and ssop packages 14 13 12 11 10 9 8 2 3 4 7 6 5 1 top view (not to scale) 17 16 15 19 18 20 28 27 26 25 24 23 22 21 ad976 ad976a v in cs busy v ana v dig agnd1 ref cap d0 (lsb) byte r/ c agnd2 d15 (msb) d14 d13 d12 d11 d3 d2 d1 d10 d9 d8 dgnd d4 d7 d6 d5 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad976/ad976a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 1.6ma i ol to output pin c l 100pf 500 m a i oh +2.1v figure 1. load circuit for digital interface timing warning! esd sensitive device
ad976/ad976a C6C rev. c pin function descriptions pin no. mnemonic description 1v in analog input. connect a 200 w resistor between v in and the analog signal source. the full-scale input range is 10 v. 2 agnd1 analog ground. used as the ground reference point for the ref pin. 3 ref reference input/output. the internal +2.5 v reference is available at this pin. alternatively, an external reference can be used to override the internal reference. in either case, connect a 2.2 m f tantalum capacitor between ref and agnd1. 4 cap reference buffer output. connect a 2.2 m f tantalum capacitor between cap and agnd2. 5 agnd2 analog ground. 6 d15 (msb) data bit 15. most significant bit of conversion result. high impedance state when cs is high or when r/ c is low. 7C13 d14Cd8 data bits 14C8. high impedance state when cs is high or when r/ c is low. 14 dgnd digital ground. 15C21 d7Cd1 data bits 7C1. high impedance state when cs is high or when r/ c is low. 22 d0 (lsb) data bit 0. least significant bit of conversion result. high impedance state when cs is high or when r/ c is low. 23 byte byte select. with byte low, data will be output as indicated above; pin 6 (d15) is the msb, pin 22 (d0) is the lsb. with byte high, the top and bottom 8 bits of data will be switched; d15Cd8 are output on pins 15C22 and d7Cd0 are output on pins 6C13. 24 r/ c read/convert input. with cs low, a falling edge on r/ c puts the internal sample/hold into the hold state and starts a conversion; a rising edge enables the output data bits. 25 cs chip select input. internally ord with r/ c . with r/ c low, a falling edge on cs will initiate a conversion. with r/ c high, a falling edge on cs will enable the output data bits. when cs is high, the output data bits will be in the hi-impedance state. 26 busy busy output. goes low when a conversion is started and remains low until the conversion is completed and the data is latched into the output register. with cs tied low and r/ c high, output data will be valid when busy rises. the rising edge of busy can be used to latch the out- put data. 27 v ana analog power supply. nominally +5 v. 28 v dig digital power supply. nominally +5 v. definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale to positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. 6 full-scale error the last + transition (from 011. . .10 to 011. . .11) should occur for an analog voltage 1 1/2 lsb below the nominal full scale (9.9995422 v for a 10 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. bipolar zero error bipolar zero error is the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. input bandwidth the input bandwidth is that frequency at which the amplitude of the reconstructed fundamental is reduced by 3 db for a full- scale input. full-power bandwidth full-power bandwidth is defined as the full-scale input fre- quency at which signal to (noise + distortion) degrades to 60 db, as 10 bits of accuracy. aperture delay aperture delay is a measure of the sample-and-hold amplifier (sha) performance and is measured from the rising edge of the clock input to when the input signal is held for a conversion.
ad976/ad976a C7C rev. c aperture jitter aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the a/d. transient response the time required for the ad976/ad976a to achieve its rated accuracy after a full-scale step function is applied to its input. overvoltage recovery the time required for the adc to recover to full accuracy after an analog input signal 150% of full-scale is reduced to 50% of the full-scale value. signal-to-(noise plus distortion ratio) (s/[n+d]) s/(n+d) is the measured signal-to-noise plus distortion ratio at the output of the adc. the signal is the rms magnitude of the fundamental. noise plus distortion is the rms sum of all of the nonfundamental signals and harmonics to half the sampling rate excluding dc. the s/(n+d) is dependent upon the number of quantization levels. the more levels, the lower the quantization noise. the theoretical s/(n+d) for a sine wave input signal can be calculated using the following: s /( n + d ) = (6.02 n + 1.76) db (1) where n is the number of bits. thus, for an ideal 16 bit converter, s/(n+d) = 98 db. the output spectrum from the adc is evaluated by applying a low noise, low distortion sine wave signal to the v in pin and sampling at a 200 khz throughput rate. by generating a fast fourier transform (fft) plot, the s/(n+d) data can then be obtained. figure 10 shows a typical 2048-point fft plot with an input signal of 45 khz and a sampling rate of 200 khz. the s/(n+d) obtained from this graph is 86.23 db. since the measured s/(n+d) is less than the theoretical value, it is possible to get a measure of performance expressed in effective number of bits (enob). enob = (( s /( n + d ) C 1.76) / 6.02) thus for an input signal of 45 khz, the typical enob is 14. total harmonic distortion (thd) thd is the ratio of the rms sum of the harmonics to the rms value of the fundamental. for the ad976/ad976a, thd is defined as: thd db vvvvv v () = ++++ 20 2 2 3 2 4 2 5 2 6 2 1 log where v 1 is the rms amplitude of the fundamental, and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through sixth harmonics. the thd is also derived from the fft plot of the adc output spectrum shown in figure 10 and is seen there as C105.33 db. spurious free dynamic range (spfd) the spurious free dynamic range is defined as the difference, in db, between the peak spurious or harmonic component in the adc output spectrum (up to f s /2 and excluding dc) and the rms value of the fundamental. normally, the value of this specification will be determined by the largest harmonic in the spectrum. the typical spfd for the ad976/ad976a is C100 db and can be seen in figure 10. functional description the ad976/ad976a is a high speed, low power, 16-bit sam- pling, analog-to-digital converter that can operate from a single +5 volt power supply. the ad976/ad976a uses laser trimmed scaling input resistors to provide an industry standard 10 volt input range. with a 100/200 ksps throughput rate and a paral- lel interface, the ad976/ad976a is capable of connecting di- rectly to digital signal processors and microcontrollers. the ad976/ad976a employs a successive-approximation technique to determine the value of the analog input voltage. instead of using the traditional laser-trimmed resistor-ladder approach, however, this device uses a capacitor array charge distribution technique. binary weighted capacitors subdivide the input sample to perform the actual analog-to-digital conversion. the capacitor array eliminates variation in the linearity of the device due to temperature-induced mismatches of resistor val- ues. as a result of having an on-chip capacitor array, there is no need for additional external circuitry to perform the sample/hold function. initial errors in capacitor matching are eliminated at the time of manufacturing. calibration coefficients are calculated that cor- rect for capacitor mismatches and are stored in on-chip thin-film resistors that act as rom. as a conversion is occurring, the appro- priate calibration coefficients are read out of rom. the accumu- lated coefficients are then used to adjust and improve conversion accu racy. any initial offset error is also trimmed out during factory calibration. with the addition of an onboard reference the ad976/ad976a provides a complete 16-bit a/d solution.
ad976/ad976a C8C rev. c data valid t 6 t 3 t 1 t 10 t 9 convert convert acquire mode data bus not valid hi-z data valid busy r/ c t 7 t 8 t 11 t 13 acquire t 2 t 4 previous data valid t 5 previous data valid t 14 hi-z figure 2. conversion timing with outputs enabled after conversion ( cs tied low) mode busy r/ c data bus cs t 6 t 12 t 1 convert acquire hi-z data valid t 7 acquire t 9 t 12 t 12 t 12 t 1 t 3 t 4 t 14 hi-z figure 3. using cs to control conversion and read timing conversion control the ad976/ad976a is controlled by two signals: r/ c and cs , as shown in figures 2 and 3. to initiate a conversion and place the sample/hold circuit into the hold state, both the r/ c and cs signals must be brought low for no less than 50 ns. once the conversion process begins, the busy signal will go low until the conversion is complete. at the end of a conversion, busy will return high, and the resulting valid data will be available on the data bus. on the first conversion after the ad976/ad976a is powered up, the data output will be indeterminate. the ad976/ad976a exhibits two modes of conversion. in the mode demonstrated in figure 2, conversion timing is controlled by a negative-going r/ c signal, at least 50 ns wide. in this mode the cs pin is always tied low, and the only limit placed on how long the r/ c signal can remain low is the desired sampling rate. less than 83 ns after the initiation of a conversion, the busy signal will be brought low and remain low until the conversion is complete and the output shift registers have been updated with the new binary twos complement data. figure 3 demonstrates the ad976/ad976a conversion timing, using cs to control both the conversion process and the reading of output data. to operate in this mode, the r/ c signal should be brought low no less than 10 ns before the falling edge of a cs pulse (50 ns wide) is applied to the adc. once these two pulses are applied, busy will go low and remain low until a conver- sion is complete. after a maximum of 4 m s (ad976a only), busy will again return high, and parallel data will be valid on the adc outputs. to achieve the maximum 100 khz/200 khz throughput rate of the part, the negative going r/ c and cs control signals should be applied every 5 m s (ad976a). it should also be noted that although all r/ c and cs commands will be ignored once a conversion has begun, these inputs can be asserted during a conversion; i.e., a read during conversion can be performed. voltage transients on these inputs could feed through to the analog circuitry and affect conversion results.
ad976/ad976a C9C rev. c r/ c cs byte pins 6C13 pins 15C22 hi-z high byte low byte hi-z hi-z high byte low byte hi-z t 14 t 12 t 12 t 14 t 9 figure 4. using cs and byte to control data bus read timing regardless of the method for controlling conversions, output data from conversion nC1 will be valid during the busy low time for roughly 3.7 m s (ad976a only), and output data from conversion n will be valid at the end of a conversion, 50 ns (t 10 ) before busy returns high. it is recommended, however, that data is read only after busy goes high since this timing is much more clearly defined and provides optimal performance. figure 4 demonstrates the functionality of the byte pin and shows how the data will be valid in binary twos complement format only when r/ c is asserted high and cs is low. the byte pin enables the output data on the bus to be read as a full parallel output or as two 8-bit bytes on pins 6C13 and pins 15C22. analog inputs figure 5 shows the analog input section for the ad976 when operating with an internal reference. the analog input range is nominally a bipolar C10 v to +10 v. since the ad976/ad976a can be operated with an internal or external reference, the full- scale analog input range can be best represented as 4 v ref . the nominal input impedance is 23 k w /13 k w with a 22 pf input capacitance. the analog input section also has a 25 v overvoltage protection. since the ad976/ad976a has two analog grounds it is important to ensure that the analog input is referenced to the agnd1 pin, the low current ground. this will minimize any problems associated with a resistive ground drop. it is also important to ensure that the analog input of the ad976/ad976a is driven by a low impedance source. with its primarily resistive analog input circuitry, the adc can be driven by a wide selection of general purpose amplifiers. to best match the low distortion requirements of the ad976/ ad976a, care should be taken in the selection of the drive circuitry op amp. figure 6 shows the analog input section for the ad976a when operating with an internal reference only. figure 9 shows the analog input section for both the ad976 and the ad976a when operating with an external reference. v in agnd1 ref cap agnd2 6 10v input r2 33.2k v c2 2.2 m f ad976 r1 200 v c1 2.2 m f figure 5. 10 v input connection for the ad976 (internal reference) c1 2.2 m f r2 66.4k v v ana v in agnd1 ref cap agnd2 6 10v input c2 2.2 m f ad976a r1 200 v +5v figure 6. 10 v input connection for the ad976a (internal reference) only
ad976/ad976a C10C rev. c offset and gain adjustment the ad976/ad976a is factory trimmed to minimize gain, offset and linearity errors. in some applications, where the ana- log input signal is required to meet the full dynamic range of the adc, the gain and offset errors need to be externally trimmed to zero. figure 7 shows the required trim circuitry to correct for these offset and gain errors. figure 8 shows the bipolar transfer characteristic of the ad976/ad976a. where adjustment is required, offset error must be corrected before gain error. to achieve this, trim the offset resistor r3 while the input voltage is 1/2 lsb below ground. by applying a voltage of C152.6 m v at the input and adjusting the potentiom- eter until the major carry transition is located between 1111 1111 1111 1111 and 0000 0000 0000 0000, the internal offset can be corrected. to adjust the gain error, an analog signal should be input at either the first code transition (adc negative full-scale) or the last code transition (adc positive full-scale). thus, to adjust for full-scale error, an input voltage of 9.999542 v (fs/2C3/2 lsbs) can be applied to the input and r4 should be adjusted until the output code flickers between the last positive code transition 0111 1111 1111 1111 and 0111 1111 1111 1110. should the first code transition need adjusting, the trim procedure should consist of applying an analog input signal of C9.999847 v (Cfs/2 + 1/2 lsb) to the input and adjusting the trim until the output code flickers between 1000 0000 0000 0000 and 1000 0000 0000 0001. the external 200 w and 33.2k resistor shown in the data sheet for the ad976 provide compensation for an internal adjustment of the offset and gain which allows calibration with a single supply. these resistors may not be required in some applications but it should be noted that their removal will result in offset and gain errors in addition to those listed in the electrical specifications of the data sheet. tables i and ii illustrate the worst case range for bipolar zero (offset) error and full-scale (gain) error for the ad976 and the ad976a. all error terms are with respect to the a/d (i.e., a negative offset in the table would have to be corrected with an externally applied positive voltage). r5 576k v +5v r4 50k v v in agnd1 ref cap agnd2 6 10v input r2 33.2k v c2 2.2 m f ad976/ ad976a r1 200 v c1 2.2 m f r3 50k v figure 7. input connection with offset and gain adjustment output code 011...111 011...110 000...001 000...000 111...111 100...010 100...001 100...000 0v (v ref /2) C 1 lsb (v ref /2) + 1 lsb + fs C 1 lsb fs = v ref v 1lsb = fs 65536 v ref /2 v in = ( ain(+) - ain(-) ) C input voltage figure 8. the bipolar transfer characteristic of the ad976/ad976a table i. offset and gain error for ad976 with both external without the external with the external 33.2k without either external error term resistors included 33.2k resistor resistor grounded resistors included offset error C10 mv < error < 10 mv C25 mv < error < C5 mv C25 mv < error < C5 mv C40 mv < error < C15 mv +full scale C0.50% < error < 0.50% 1 C0.05% < error < 0.95% C0.65% < error < 0.35% 0.55% < error < 1.90% error C0.25% < error < 0.25% 2 Cfull scale C0.50% < error < 0.50% 1 0.25% < error < 1.25% C0.65% < error < 0.35% C2.5% < error < C1.0% error C0.25% < error < 0.25% 2 table ii. offset and gain error for ad976a with both external without the external with the external 33.2k without either external error term resistors included 33.2k resistor resistor grounded resistors included offset error C10 mv < error < 10 mv C25 mv < error < C5 mv C25 mv < error < C5 mv C55 mv < error < C25 mv +full scale C0.50% < error < 0.50% 1 C0.05% < error < 0.95% C0.65% < error < 0.35% 1.0% < error < 2.50% error C0.25% < error < 0.25% 2 Cfull scale C0.50% < error < 0.50% 1 0.25% < error < 1.25% C0.65% < error < 0.35% C3.50% < error < C1.75% error C0.25% < error < 0.25% 2 notes 1 for a grade part. 2 for b grade part.
ad976/ad976a C11C rev. c voltage reference the ad976/ad976a has an on-chip temperature compensated bandgap voltage reference that is factory trimmed to 2.5 v 20 mv. the full-scale range of the adc is equal to 4v ref . thus, the nominal range will be 10 v. the accuracy of the ad976 over the specified temperature range is dominated by the drift performance of the voltage refer- ence. the on-chip voltage reference is laser-trimmed to provide a typical drift of 7 ppm/ c. this typical drift characteristic is shown in figure 13, which is a plot of the change in reference voltage (in mv) versus the change in temperaturenotice the plot is normalized for zero error at +25 c. if improved drift performance is required, an external reference such as the ad780 should be used to provide a drift as low as 3 ppm/ c. in order to simplify the drive requirements of the voltage reference (internal or external), an onboard reference buffer is provided. the output of this buffer is provided at the cap pin and is available to the user; however, when externally loading the refer- ence buffer, it is important to make sure that proper precautions are taken to minimize any degradation in the adcs perfor- mance. figure 14 shows the load regulation of the reference buffer. notice that this figure is also normalized so that there is zero error with no dc load. in the linear region, the output im- pedance at this point is typically 1 ohm. because of this 1 ohm output impedance, it is important to minimize any ac or input dependent loads that will lead to increased distortion. any dc loads will simply act as a gain error. although the typical char- acteristic of figure 14 shows that the ad976 is capable of driv- ing loads greater than 15 ma, it is not recommended that the steady state current exceed 2 ma. in addition to the on-chip reference, an external 2.5 v reference can be applied. when choosing an external reference for a 16-bit application, however, careful attention should be paid to noise and temperature drift. these critical specifications can have a significant effect on the adc performance. figure 9 shows the ad976/ad976a with the ad780 voltage reference applied to the ref pin. the ad780 is a bandgap reference that exhibits ultralow drift, low initial error, and low output noise. for low power applications, the ref192 provides a low quiescent current, high accuracy and low temperature drift solution. c4 0.1 m f v ana c3 1 m f v in agnd1 ref cap agnd2 6 10v input r2 33.2k v c2 2.2 m f ad976/ ad976a r1 200 v c1 2.2 m f ad780 gnd v out temp v in 0.1 m f +5v figure 9. ad780 external reference connection to the ad976/ad976a ac performance the ad976/ad976a is fully specified and tested for dynamic performance specifications. the ac parameters are required for signal processing applications such as speech recognition and spectrum analysis. these applications require information on the adcs effect on the spectral content of the input signal. hence, the parameters for which the ad976/ad976a is speci fied include: s/(n+d), thd and spurious free dynamic range. these terms are discussed in greater detail in the follow- ing sections. as a general rule, it is recommended that the results from sev- eral conversions be averaged to reduce the effects of noise, thus improving parameters such as s/(n+d) and thd. the ac per- formance of the ad976/ad976a can be optimized by operating the adc at its maximum sampling rate of 100 khz/200 khz and by digitally filtering the resulting bit stream to the desired signal bandwidth. by distributing noise over a wider frequency range, the noise density in the frequency band of interest can be reduced. for example, if the required input bandwidth is 50 khz, the ad976a could be oversampled by a factor of 2. this would yield a 3 db improvement in the effective snr performance. frequency C khz 0 C10 C150 0 100 10 20 30 40 C40 C70 C130 C140 C20 C30 C60 C50 db C90 C120 C80 C110 C100 50 60 70 80 90 95 5 1525354555657585 f sample = 200khz f in = 45khz snr = 86.23db thd = C105.33db 100% figure 10. fft plot dc performance the factory calibration scheme used for the ad976/ad976a compensates for bit weight errors that may exist in the capacitor array. the mismatch in capacitor values is adjusted (using the calibration coefficients) during a conversion, resulting in excellent dc linearity performance. figures 11, 12, 15, 16, 17 and 18, respectiv ely, show typical inl, typical dnl, typical positive and negative inl and dnl distribution plots for the ad976/ad976a at +25 c. a histogram test is a statistical method for deriving an a/d converters differential nonlinearity. a ramp input is sampled by the adc and a large number of conversions are taken and stored. theoretically, the codes would all be the same size and therefore have an equal number of occurrences. a code with an average number of occurrences would have a dnl of 0. a code that is different than the average would have a dnl that was either greater or less than zero lsb. a dnl of C1 lsb indicates that there is a missing code present at the 16-bit level and that the adc exhibits 15-bit performance.
ad976/ad976a C12C rev. c output code C k 066 5 101520253035 2.0 C2.0 0 C0.5 C1.0 C1.5 1.0 0.5 1.5 40 45 50 55 60 100% lsb figure 11. inl plot output code C k 0 66 5 101520253035 2.0 C2.0 0 C0.5 C1.0 C1.5 1.0 0.5 1.5 40 45 50 55 60 100% lsb figure 12. dnl plot degrees celsius C55 1mv/div 25 125 figure 13. reference drift load current C 5ma/div dv on cap pin C 10mv/div source capability sink capability figure 14. cap (pin 4) load regulation 90 80 0 50 40 30 70 60 20 10 number of units 0 0.2 0.3 0.4 0.6 0.7 0.8 1.0 1.1 1.2 1.4 1.5 1.6 1.8 1.9 2.0 2.2 2.3 2.4 2.6 2.7 2.8 3.0 3.1 3.2 positive inl distribution C lsb figure 15. typical positive inl distribution (1516 units) 90 0 70 60 50 40 80 10 number of units C2.5 C0.4 C0.3 C0.2 C0.1 negative inl distribution C lsb C2.4 C2.3 C2.2 C2.1 C2.0 C1.9 C1.8 C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0 C0.9 C0.8 C0.7 C0.6 C0.5 20 30 figure 16. typical negative inl distribution (1516 units)
ad976/ad976a C13C rev. c dc code uncertainty ideally, a fixed dc input should result in the same output code for repetitive conversions; however, as a consequence of un- avoidable circuit noise within the wideband circuits of the adc, a range of output codes may occur for a given input voltage. thus, when a dc signal is applied to the ad976/ad976a input, and 10,000 conversions are recorded, the result will be a distri- bution of codes as shown in figure 19. this histogram shows a bell-shaped curve consistent with the gaussian nature of ther- mal noise. the histogram is approximately seven codes wide. the standard deviation of this gaussian distribution results in a code transition noise of 1 lsb rms. 4000 3500 0 C3 2000 1500 1000 500 3000 2500 C2 C1 0 1 2 3 4 figure 19. histogram of 10,000 conversions of a dc input microprocessor interfacing the ad976/ad976a is ideally suited for traditional dc mea- surement applications supporting a microprocessor and ac signal processing applications interfacing to a digital signal processor. the ad976/ad976a is designed to interface with a 16-bit data bus and provides all output data bits in a single read cycle. a variety of external buffers can be used with the ad976/ad976a to prevent bus noise from coupling into the adc. the following sections illustrate the use of the ad976/ad976a with the mc68000 and 8051 microcontrollers and the tms320c25 and adsp-2111 signal processors. mc68000 interface figure 20 shows a general interface diagram for the mc68000 16-bit microprocessor to the ad976/ad976a. in figure 20, conversion is initiated by bringing csa low (i.e., writing to the appropriate address). this allows the processor to maintain control over the complete conversion process. address bus *additional pins omitted for clarity data bus db15 db0 busy ad976/ ad976a r/ c bus 74hc374 oe q15 q0 d0 d15 clk en addr decode a0 a15 d15 d0 68000 r/w as figure 20. ad976/ad976a to 68000 interface 250 0 150 100 200 50 number of units 0 0.2 0.3 0.4 0.6 0.7 0.8 1.0 1.1 1.2 1.4 1.5 1.6 1.8 1.9 2.0 2.2 2.3 2.4 2.6 2.7 2.8 3.0 3.1 3.2 positive dnl distribution C lsb figure 17. typical position dnl distribution (1516 units) 140 0 80 20 120 100 number of units C1.2 negative dnl distribution C lsb 60 40 C1.2 C1.1 C1.1 C1 C1 C0.9 C0.9 C0.8 C0.8 C0.7 C0.7 C0.6 C0.6 C0.5 C0.5 C0.4 C0.4 C0.3 C0.3 C0.2 C0.2 C0.1 C0.1 0 0 figure 18. t ypical negative dnl distribution (1 516 units)
ad976/ad976a C14C rev. c 8051 interface figure 21 illustrates the use of the ad976/ad976a with an 8051 microcontroller. db7 db0 byte a0 cs bus *additional pins omitted for clarity busy ad976/ ad976a 8051 latch bus bus ad0 ad7 p0 a15 a8 p2 rd wr int r/ c addr decode figure 21. ad976/ad976a to 8051 interface tms320c25 interface figure 22 shows an interface between the ad976/ad976a and the tms320c25. timer address bus *additional pins omitted for clarity data bus db15 db0 busy ad976/ ad976a r/ c en addr decode a0 a15 d15 d0 tms320c25 r/w is ready strb nsc int cs figure 22. ad976/ad976a to tms320c25 interface adsp-2111 interface figure 23 shows an interface to the adsp-2111 signal processor. in this example, cs is being used to control conversions and is generated by an external timer. a conversion is initiated each time the timer output goes low as long as you are not reading from the ad976/ad976a and while the flag output (fo) pin of the adsp-2111 is low. when a conversion is complete, the busy line will return high. with the irqn pin programmed to generate an interrupt on a high-to-low transition, an interrupt will occur at the end of each conversion. the 16-bit result of the conversion can be read from within the interrupt service routine by first forcing fo high, then performing a read operation with the ad976/ad976a. address bus *additional pins omitted for clarity data bus db15 db0 busy ad976/ ad976a en addr decode a0 a13 d15 d0 adsp-2111 dms irqn cs timer rd fo r/ c figure 23. ad976/ad976a to adsp-2111 interface power supplies and decoupling the ad976/ad976a has two power supply input pins. v ana and v dig provide the supply voltages to the analog and digital portions, respectively. v ana is the +5 v supply for the on-chip analog circuitry, and v dig is the +5 v supply for the on-chip digital circuitry. the ad976/ad976a is designed to be inde- pendent of power supply sequencing and, thus, free from supply voltage induced latch-up. with high performance linear circuits, changes in the power supplies can result in undesired circuit performance. optimally, well regulated power supplies should be chosen with less than 1% ripple. the ac output impedance of a power supply is a complex function of frequency and it will generally increase with frequency. thus, high frequency switching, such as that encoun- tered with digital circuitry, requires the fast transient currents that most power supplies can not adequately provide. such a situation results in large voltage spikes on the supplies. to com- pensate for the finite ac output impedance of most supplies, charge reserves should be stored in bypass capacitors. this will effectively lower the supplies impedance presented to the ad976/ad976a v ana and v dig pins and reduce the magnitude of these spikes. decoupling capacitors, typically 0.1 m f, should be placed close to the power supply pins of the ad976/ad976a to minimize any inductance between the capacitors and the v ana and v dig pins. the ad976/ad976a may be operated from a single +5 v sup- ply. when separate supplies are used, however, it is beneficial to have larger capacitors, 10 m f, placed between the logic supply (v dig ) and digital common (dgnd) and between the analog supply (v ana ) and the analog common (agnd2). additionally, 10 m f capacitors should be located in the vicinity of the adc to further reduce low frequency ripple. in systems where the device will be subjected to harsh environmental noise, additional de- coupling may be required.
ad976/ad976a C15C rev. c grounding the ad976/ad976a has three ground pins; agnd1, agnd2 and dgnd. the analog ground pins are the high quality ground reference points and should be connected to the system analog common. agnd2 is the ground to which most internal adc analog signals are referenced. this ground is most suscep tible to current induced voltage drops and thus must be connected with the least resistance back to the power supply. agnd1 is the low current analog supply ground and should be the analog common for the external reference, input op amp drive circuitry and the input resistor divider circuit. by applying the inputs referenced to this ground, any ground variations will be offset and have a minimal effect on the resulting analog input to the adc. the digital ground pin, dgnd, is the reference point for all of the digital signals that control the ad976/ad976a. the ad976/ad976a can be powered with two separate power supplies or with a single analog supply. when the system digital supply is noisy or fast switching digital signals are present, it is recommended to connect the analog supply to both the v ana and v dig pins of the ad976/ad976a and the system supply to the remaining digital circuitry. with this configuration, agnd1, agnd2, and dgnd should be connected back at the adc. when there is significant bus activity on the digital output pins, the digital and analog supply pins on the adc should be sepa- rated. this would eliminate any high speed digital noise from coupling back to the analog portion of the ad976/ad976a. in this configuration, the digital ground pin dgnd should be connected to the system digital ground and be separate from the agnd pins. board layout designing with high resolution data converters requires careful attention to board layout. trace impedance is a significant issue. a 1.22 ma current through a 0.5 w trace will develop a voltage drop of 0.6 mv, which is 2 lsbs at the 16-bit level over the 20 volt full-scale range. ground circuit impedances should be reduced as much as possible since any ground potential differ- ences between the signal source and the adc appear as an error voltage in series with the input signal. in addition to ground drops, inductive and capacitive coupling needs to be considered. this is especially true when high accuracy analog input signals share the same board with digital signals. thus, to minimize input noise coupling, the input signal leads to v in and the signal return leads from agnd should be kept as short as possible. in addition, power supplies should also be decoupled to filter out ac noise. analog and digital signals should not share a common path. each signal should have an appropriate analog or digital return routed close to it. using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. wide pc tracks, large gauge wire and ground planes are highly recom- mended to provide low impedance signal paths. separate analog and digital ground planes are also recommended with a single interconnection point to minimize ground loops. analog signals should be routed as far as possible from high speed digital sig- nals and should only cross them, if absolutely necessary, at right angles. in addition, it is recommended that multilayer pc boards be used with separate power and ground planes. when designing the separate sections, careful attention should be paid to the layout.
C16C c2624cC1C8/99 printed in u.s.a. ad976/ad976a rev. c 28-lead 300 mil plastic dip (n-28b) 28 1 14 15 pin 1 1.425 (36.195) 1.385 (35.179) 0.280 (7.11) 0.240 (6.10) 0.015 (0.381) min 0.210 (5.33) max 0.150 (3.81) 0.115 (2.92) seating plane 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.014 (0.356) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 28-lead soic (r-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 28 15 14 1 28-lead ssop (rs-28) 28 15 14 1 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0 outline dimensions dimensions shown in inches and (mm).
package/price information 16-bit, 200 ksps, parallel i/o a/d converter * this price is provided for budgetary purposes as recommended list price in u.s. dollars per unit in the stated volume. pricing displayed for evaluation boards and kits is based on 1-piece pricing. view pricing and availability for further information. model status package description pin count temperature range price* (100-499) ad976aachips production chips/die sales - military $30.59 ad976aan production plastic/epoxy dip 28 industrial $30.59 ad976aar production std s.o. pkg (soic) 28 commercial $30.59 ad976aars production shrink so package 28 industrial $30.59 ad976aarsrl production shrink so package 28 industrial - ad976abn production plastic/epoxy dip 28 industrial $38.24 ad976abr production std s.o. pkg (soic) 28 industrial $38.24 ad976abrs production shrink so package 28 industrial $38.24 ad976abrsrl production shrink so package 28 industrial - ad976acn production plastic/epoxy dip 28 industrial $26.74 ad976acr production std s.o. pkg (soic) 20 commercial $26.74 ad976acrs production shrink so package 28 industrial $26.74

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